The present invention relates to microelectronic circuit substrates including active integrated circuits and passive integrated circuits, and microelectronic wiring substrates, and more particularly to conductive interconnects therein.
Integrated circuits (“ICs” or “chips”) can be categorized according to function and the devices they contain, i.e., into active chips which contain active elements such as transistors, and/or other gain devices including diodes, and passive chips which contain only passive elements, e.g., capacitors, inductors and/or resistors. Microelectronic wiring substrates, especially multi-layer wiring substrates, are sometimes used to provide fine pitch or relatively fine pitch wiring for interconnecting a relatively high number of external terminals of one chip to other devices and/or another chip. Within such microelectronic wiring substrates and chips, electrical interconnection is provided using conductive interconnects.
Whether on active chips, passive chips or microelectronic wiring substrates, conductive interconnects are subject to fail due to stresses which occur at times when such chips or wiring substrates are installed in end products for their intended use. Stresses due to the accumulated effects of heating chips during their use lifetimes can contribute to a particular failure mechanism known as thermo-mechanical stress degradation or stress-induced voiding. When a chip is heated for a prolonged accumulated time, e.g., such as due to heat generated internally by the chip or by devices and/or other chips near the subject chip, the structure of conductive interconnects of the chip are subject to change. A void may form at a location which degrades the conductivity of the electrical interconnect structure. Alternatively, or in addition thereto, conductive material from one portion of one interconnect structure may travel or diffuse outside of intended boundaries, causing the degree of isolation between the one interconnect structure and another interconnect structure to become degraded, e.g., leading to a “short circuit” condition. Both of these types of failures can be attributed to thermo-mechanical stress degradation or stress-induced voiding.
Copper interconnects used in advanced semiconductor chips are vulnerable to thermo-mechanical stress degradation. Copper interconnects are typically formed by damascene processing (or dual damascene processing in which the vias and lines are formed in the same step) in which copper is deposited into openings in a prior-formed dielectric layer, after which excess copper is removed from the surface of the dielectric layer. The dielectric layer typically consists essentially of an oxide, such as silicon dioxide (SiO2), carbon-doped oxide (SiCOH) or a polymer having desirable dielectric properties such as a low dielectric constant (low-k) dielectric. Due to the differing physical properties of the copper and the dielectric layer, there exists a mismatch between the coefficient of thermal expansion (“CTE”) of the copper and the CTE of the dielectric layer. When the temperature of a chip is raised or lowered, CTE mismatch causes forces to be exerted on the interconnect metal relative to the dielectric material, in turn causing internal bending and/or cleaving within the interconnect and the surrounding dielectric material. Over time, the bending and cleaving leads to the above-described problems of degraded conductivity and increased incidence of short circuiting between conductive interconnects.
Another result of thermo-mechanical stress degradation is a tendency for voids to form at junctions between horizontally oriented conductive features such as metallic plates or lines, and conductive vias which provide vertical interconnection to the horizontal features. Metal features can be deposited by a process of plating (typically electroless plating followed by electroplating) sputtering, or alternatively, various processes of chemical vapor deposition (“CVD”). The deposition proceeds by the accumulation of individual grains of the metal on the underlying substrate. During such deposition, vacancies are trapped within the deposited metal. Vacancies are locations within a crystal lattice where individual atoms are missing. When a chip or wiring substrate containing metal features is maintained at a relatively high temperature for a sufficient amount of time, a thermo-mechanical stress is exerted upon the metal. Under such stress, vacancies move towards places where stress is concentrated and aggregate in those places to form voids. Locations where conductive vias connect to a metal plate or metal line are common points of failure where voids tend to form.